eFPGA IP Cores v5

Building flexible SoCs

 

 

Menta eFPGAs are high-density embedded programmable logic IPs for use in SoCs or ASICs designed to address various markets and applications.

At Menta, we believe that different problems require different solutions. Therefore, our customers can define the exact resources required for their application. 

Menta eFPGA IP Cores are organized in families based on the number of
Logic Cells (LC)avalaible: Small for 12 to 2K LC, Medium for 2K to 6K LC, Large for 6K to 60K LC and eXtra Large for 60K to 200K LC.

The table below provide examples of eFPGA that can be provided. Every element of the eFPGA can be defined in numbers: logic cells, MAC, CDSP, SRAM (type and amount) and IOs. For more information on each of these elements, refer to the
Technology section.

In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.

The eFPGA IP Cores are provided as hard IPs (GDSII). Other models are possible, contact us for more information.

Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.

Origami Designer is available to help defining the eFPGA IP targeting customer requirements.

For potential customers and partners evaluating Menta’s technology, we provide the 
Menta Starter Pack (MSP) and an evaluation board.

Download our Products Briefs to circulate to your teams:
eFPGA core IP and Origami Designer & Origami Programmer.