Building flexible SoCs

Menta eFPGA IPs and COT FPGAs share several similar aspects:

  • Core technology of look-up-tables

  • Embedded DSP processing

  • Embedded user memory

  • Configuration memory to store the bitstream

  • Routing network

  • Programming flow from RTL to bistream that includes synthesis and place & route

There are also many different aspects that are summarized in the below table :

20x bandwidth increase and 30x latency reduction



The aspects summarized in the abovetable lead to three different advantages for eFPGA IPs over FPGAs: improved performances, reduced power consumption and reduced cost.

In addition to being deterministic in nature, like FPGAs, the eFPGA IPs are not limited by the chip package :
- direct connection of the eFPGA to embedded memories, CPUs, buses or other IPs allow a latency in the order of 1ns while most expensive FPGA devices allow for a latency in the order of 30 to 50ns
- the number of data pins available can be more than 20x the ones of the most expensive FPGAs. That directly translates in a bandwidth increase of around 20x too.

2x to 10x power consumption reduction

In a COT FPGA, all the extra to the programmable logic, such as high speed interfaces, PLL, controllers, etc. consume around half of the power. 

An eFPGA will also use less LUTs than a FPGA:
 - all the protocols management can be hardcoded in the ASIC
 - only the portions of the algorithms that really needs the programmability are placed on LUTs; the rest is to made in ASIC
 - Menta eFPGA IPs offer a LUTs utilization in excess of 90%, compared to generally ~70% for FPGAs

Using an eFPGA IP in a SOC or ASIC also allows removing the extra components required on a board for a FPGA such as dedicated DDR, coupling capacitances, PMU, etc. 

All this combined effects lead an algorithm on a Menta eFPGA IP to consume between 10 and 50% of the power of the same algorithm on a FPGA.

Cost reduction

Menta eFPGA IP offers a potentially strong cost reduction :

 - due to their high price, FPGAs are still most of the time used for prototyping or low volume production. When a mid to high volume is required, the high NRE of doing a SoC / ASIC is diluted and the economy is now in favor of producing chips. With Menta eFPGA IPs, you can retain some of the FPGA flexibility in your high volume product.

 - reduction of the BoM (Bill of Material) by removing extra components for FPGA power up, bitstream loading and interaction with the SoC on the board. The board area is also reduced.


When to use a Menta eFPGA IP instead of a FPGA


eFPGA IPs are not replacement for FPGAs. There are little overlaps in terms of applications and markets. 
Menta eFPGA IPs are alternative to FPGAs in the following case:
- moving from prototyping / low volume FPGAs designs to mid to high volume SoC/ASIC design with a need to retain some flexibility
- requirement for very low latency / high bandwidth and either highly parrallel computation, flexibility or determinism
- achieving specific designs for which no COT FPGA exist
- specific chips / projects for which COTs chips cannot be used