Why choose a Menta eFPGA IP
An eFPGA IP combines both FPGA and IP requirements characteristics. Based on 10+ years of experience, Menta made strong engineering choices to fulffill both requirements.
Power, Performances, Area
Menta IPs benefit of 10+ years of R&D with research on LUTs, interconnects and programming software.
Contrary to what some of our competitors are claiming, Menta v5 eFPGA IPs PPA are very similar to the ones of our competitors. We have customers feedbacks we can share and we invite you to evaluate our technology against competition.
Competition solutions such as using full or some custom cells, hierarchical architecture or abutting cells have been explored by Menta more than 5 years ago. We experienced the drawbacks of these options and we went through innovations to avoid those with an improved solution.
In addition, our eFPGA can make use of all the possibilities offered by the technology and the target standard cells to offer the full spectrum of PPA based on number of track, threshold voltages, power supply, etc. options
Portability and Time To Market
Menta eFPGA IPs are the only IPs 100% based on 3rd party standard cells. As such our IPs are foundry and process nodes independant. The GDS II can be delivered in 1 to 5 months in any process node. Other business models are possible. Contact us for more information.
While the standard cells approach allow us to avoid the hurdle of tapeouting every variants of our eFPGA IPs, we have done more than 10 tapeouts at 3 different foundries and on 5 different technology nodes, from 130nm to 14nm - on planar, SOI and FinFET CMOS. All of them first time right while delivered in very short time.
Menta eFPGA IPs are also qualified on GLOBALFOUNDRIES® 32SOI and 14LPP nodes and we are a member of the 22 FDXcelerator (TM) Partner Program.
Menta is also regularly invited at TSMC symposium and OIP.
Flexibility - application specific eFPGA IPs
While FPGAs are targeting the highest possible flexibility to accomodate for any application, we see eFPGA as application specific FPGA IPs. We believe each application and customer require a slighlty if not highly different eFPGA IP core.
Therefore, we provide application specific eFPGA IPs. This way, our customers can get the best PPA for their application by using the right arithmetic blocks or, for e.g., 128Kb of SP SRAM memory when they do not need 1Mb true DP memory.
To achieve this, our eFPGA IPs have the highest possible flexibility in their specifications as described here. We are even able to embedd customers arithmetic blocks.
Application specific eFPGA IPs allow to strongly reduce the eFPGA area overhead while keeping the right amount of flexibility in your SoC / ASIC.
ASIC / SoC & EDA flow integration
Thanks to our 100% 3rd party standard cells approach, our eFPGA IP behaves like any logic IP in terms of integration.
- The integration can be done through any standard logic design EDA flow.
- We do not require any specific interface to connect the eFPGA IP to buses, chips IO or other IPs.
- The IP can make use of any metal stack and front end and back end options.
- ASIC techniques can be applied for power management. Ask for our application note on this topic for details.
- Power grid can re-use customer power grid, avoiding the extra cost of a seal ring around the IP.
Verification, simulation and emulation
Formal verification can be applied from one end to the other to our eFPGA IPs.
Behavourial and gate level simulations can be performed, including bitstream loading verification through simulation.
Last, it is possible to emulate our eFPGA IPs on... FPGAs.
Ask for our verification and simulation documentation for details.
Menta has developped a unique and patented way to offer a standard scan chain test stuck-at-fault with a test coverage in excess of 99.8% and a fault coverage in excess of 99.5%, while adding no extra area to our eFPGA IPs.
The eFPGA IP can be tested just like the rest of the SoC / ASIC logic - with a limited test cost.
Reliability & Yield
6T SRAM bitcells are inherently subject to reliability issues such as soft errors.
In addition, they are highly sensitive to process defect density, strongly limiting the yield. In a SRAM array from a memory compiler, redundant columns of SRAM are added to achieve the targeted yield. FPGA configuration 6T STRAM bitcells need to be accessed all the same time. Therefore, the trick of adding redundant columns does not work. eFPGA providers using 6T SRAM cells must therefore limit the optimization of their custom 6T SRAM bitcells to avoid dropping the yield of the SoC that will embedd the eFPGA IP. This is strongly limiting the area efficiency of such 6T SRAM bitcells.
Menta eFPGA IPs solve both the soft errors issue and the yield issue by making use of flip-flops instead of SRAM cells.
Menta eFGPA IP yield is the same as any other logic functions on the SoC / ASIC.
Menta programming software, Origami Programmer, benefits of 120+ man years of R&D. See the dedicated page for more information.
Our Origami tool suite allows a very optimal timing driven mapping of the RTL application on the eFPGA without any EDIF translation or third party dependency.
Legal issues free
FPGA innovation is a mined field with the strong players of COT FPGAs.
At every stage of its development, Menta has taken care to not infringe any existing patent. Verification of existing patents, with the help of specialized lawyers, is a mandatory step since years for any of our R&D engineers.
Thanks to our 100% standard cells approach and the usage of flip-flop to store the bitstream, using Menta eFPGA comes with no risk as everything can be easily verified at every stage of the SoC / ASIC design.
Smaller NVM and programming time
Our eFPGA IPs architecture and programming style have been worked out to minimize our bitstream size; which is typically 2x to 4x smaller than the one of our competitors. That allows reducing the amoung of NVM required to store the bitstream but also decrease the programming time at start up - especially for our customers who encrypt / decrypt the bitstream.
Our team comprises highly experienced engineers both in hardware and software developments. Our R&D engineers and FAEs have an average experience of 19 years in EDA SW development, FPGA and ASIC/SoC design. They have been working at companies such as Xilinx, Cadence Design Systems, Texas Instruments, Intel, Infineon, Atmel, Samsung, eSilicon, UbiSoft, Elsys Design, Safran, Thales, Silicon Mobility, etc.