D&R IP-SoC Silicon Valley brings together semiconductor IP providers, SoC architects, and industry leaders to explore the latest innovations shaping IP-based electronic systems. As a key international event dedicated to silicon intellectual property, it offers a platform to discuss emerging architectural trends, showcase advanced technologies, and engage with the global semiconductor ecosystem.
At this year’s event, Menta will contribute to the discussion with a focused session:
“Why Aren’t You Considering eFPGA for Your Next ASIC? (And What It’s Costing You)”
Presented by Jayson Bethurem, who brings over 30 years of experience across FPGA and eFPGA ecosystems, the session will address a growing industry challenge: how to design silicon that can adapt over time.
If your ASIC cannot evolve, it will age the day it is deployed. In a context where silicon lifecycles extend over decades while requirements evolve in months, adaptability is no longer optional — it is becoming a core architectural requirement.
Menta looks forward to engaging with the IP and SoC community in Santa Clara and contributing to the next generation of adaptable silicon platforms.
