Menta Starter Pack

Menta Starter Pack: Your Gateway to eFPGA Innovation

Accelerate Your eFPGA Experience with the Menta Starter Pack (MSP)

Why Choose the Menta Starter Pack

The Menta Starter Pack (MSP) offers an ideal opportunity to delve deep into the intricacies of eFPGA technology and kickstart your design process. This comprehensive package encompasses two days of immersive training sessions, which can be conveniently conducted either at your location or at Menta’s headquarters in Sophia-Antipolis, France.

Unpacking the Menta Starter Pack

Throughout the training program, our experts meticulously cover all facets of the technology, providing in-depth insights into eFPGA architectures, implementation methodologies, simulation techniques, and testing strategies. Upon the conclusion of the training sessions, participants gain exclusive access for six weeks to Origami Programmer, a powerful tool for eFPGA development, along with a collection of sample RTL designs to facilitate hands-on exploration.

Getting Started with the Menta Starter Pack

Additionally, our dedicated Field Application Engineers (FAEs) stand ready to provide personalized support and guidance, ensuring a seamless transition from training to practical application of eFPGA technology in your projects.

With the Menta Starter Pack, you’re equipped with the knowledge, tools, and support needed to embark confidently on your eFPGA design journey.

Advantages of Using Menta’s eFPGA Product benefits

Complete Static Timing Analysis Report

SDC files support

Performance estimation based on selected technology node and libraries

Reports on critical paths

Generation of setup and hold report

Embedded RTL parser and synthesis

IEEE VHDL, Verilog and System-Verilog support

Synthesized RTL designs optimized to Menta eFPGA architecture

High efficiency

Target any Menta eFPGA resources and optimize for those

Place & Route

Powerful Place & Route engine

Low LUT usage and Optimum routing

Timing and IO placement constraints aware

Timing driven

Floor planning

User-friendly Graphical Interface

Resource usage summary within GUI or as an ASCII file

Statistics on density

Entirely scriptable in TCL

Complete Static Timing Analysis Report

SDC files support

Performance estimation based on selected technology node and libraries

Reports on critical paths

Generation of setup and hold report

Embedded RTL parser and synthesis

IEEE VHDL, Verilog and System-Verilog support

Synthesized RTL designs optimized to Menta eFPGA architecture

High efficiency

Target any Menta eFPGA resources and optimize for those

Place & Route

Powerful Place & Route engine

Low LUT usage and Optimum routing

Timing and IO placement constraints aware

Timing driven

Floor planning

User-friendly Graphical Interface

Resource usage summary within GUI or as an ASCII file

Statistics on density

Entirely scriptable in TCL

menta

Case studies

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