Verific Design Automation builds SystemVerilog, VHDL, and UPF Parser Platforms which enable its customers to develop advanced EDA products quickly and at low cost. Verific’s Parser Platforms are distributed as C++ source code and compile on all 32 and 64 bit Unix, Linux, Mac, and Windows operating systems. Verific’s Parser Platforms are in production and development use at numerous companies worldwide, from start-ups to established EDA, FPGA, semiconductor, and system vendors.
