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Adaptive Digital Signal Processor

Menta’s Adaptive Digital Signal Processor (DSP) solution can be inferred automatically using Menta Origami tool suite within the user’s embedded FPGA (eFPGA). The Adaptive Menta DSP solution will allow users to implement the ideal DSP architecture within the eFPGA IP that better suits the hardware requirement. 

 
​Operand size can be chosen for both the multiplier and the arithmetic logic unit (ALU). 
The DSP block operating modes are programmable through the bitstream. It can dynamically be reconfigurable, and its behavior can be controlled at clock cycle level. 
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DSP configuration is made easy through Origami Designer eFPGA IP software graphical interface and the adaptive DSP is automatically inferred by Origami Programmer synthesis within your eFPGA IP.
A Menta FIR generator empowers users to generate RTL code of an optimized FIR using Menta patented DSP FIR engine. The range of the FIR supported can be set between 4 and 512 taps, allowing users to define the number of DSP to use within their architecture as well as the data bus, and the ALU size, helping users meet frequency, area and latency goals.

Download the Adaptive Digital Signal Processor product brief to circulate to your teams and learn more about its features and benefits

Menta delivers 100% third party standard-cells embedded FPGA IPs for SoC, ASIC or ASSP designs. 

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Phone: +33 (0) 9 72 41 03 10

Fax: +33 (0) 9 72 11 33 65

Menta S.A.S, Sophia Antipolis

Les Drakkar, 2405 route des Dolines

06560 Valbonne

France