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Edge Servers & HPC

For ASIC and SoCs designers who need to deploy, monitor and manage edge computing and high performance computing (HPC) resources efficiently and effectively, Menta is the proven eFPGA pioneer.  Menta’s design-adaptive standard cells based architecture and state-of-the-art tool set provides the highest degree of design customization, best-in-class testability and fastest time-to-volume for SoC design targeting any production node at any foundry.



AI learning accelerator

FPGAs have demonstrated their superior energy efficiency over CPUs and GPUs for AI learning in data centers and are already being used by multiple players. eFPGA IPs from Menta take this one step further by introducing AI learning accelerators within the CPU chip. This allows users to obtain the best performance, area and power consumption by integrating complex arithmetic blocks, such as high precision, floating-point DSPs, while also benefitting from the smallest possible latency and highest possible throughput.

Cryptography accelerators

FPGA COT components are often used as cryptography (AES, SHA, etc.) accelerators. However, this introduces risk of compromising the entire system’s security by hacking the communication between the ASIC/SoC and the COT component. eFPGA IPs offer a great way to overcome the issue by integrating the reconfigurable configuration within the ASIC/SoC.



For High Performance Computing (HPC) applications, in many cases having one or two more instructions available within the central processing unit (CPU) instructions set can strongly accelerate the application runtime and decrease power consumption. Today, this can be achieved by integrating Menta eFPGA IP within the CPU’s datapath. Menta programming software is available as an API for easy sharing with end customers.



In the near future, a new form of non-volatile memories (NVMs) will emerge and possibly replace flash-based SSD drives. Using an eFPGA as an SSD controller interface allows the interface to evolve for future protocols.

5G base stations evolving standard

5G base station standards are still evolving as 5G networks are being deployed. By integrating the right amount of flexibility within a 5G base station chip, such as 5G pico cells, users can avoid using high cost FPGAs.



Advanced node designs such as 7nm typically cost between $30 million and $50 million. Using eFPGA IPs allows users to incorporate algorithms that help avoid risk of re-spin.



Design adaptive eFPGA IP
100% standard cells architecture
Foundry and process node independent
Proven on advanced nodes
No change in EDA flow
RTL to bitstream software as an API
HLS programming with third party tools
Strong simulation and verification flow
Integration of any kind of arithmetic block
Adaptive DSPs blocks
Integration of any third-party memory
State-of-the-art eFPGA EDA programming tool
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