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Edge Computing / IoT

Security is important in edge computing and IoT technology and running encryption/decryption algorithms on Menta eFPGA IPs allow the algorithms to be updated in the field saving precious time and resources. Designers can also reconfigure MCU in the field, reducing supply chain and number variants.

Programmable logic cost can be reduced by up to 10x by reducing BoM, getting rid of tiny FPGAs that are used for interfaces and last-minute fixes by embedding the logic in your IoT SoC.

Designers can also support new sensors and applications in the field with high power efficiency with sensor hub.

 

Applications

Cryptography

Whenever security is important, running encryption / decryption algorithms on Menta eFPGA IPs allows these algorithms to be updated in the field.

Reconfigurable MCU

Reduce supply chain and number of variants. Reconfigurable MCUs in the field.

Reducing BoM

Get rid of the tiny FPGAs that are used for interfaces and last minutes fixes by embedding the logic in your IoT SoC. Programmable logic cost can be reduced by up to 10x.

Smart sensors

Using eFPGAs to replace glue logic functions allow reducing the number of variants so the same chip can be delivered to multiple markets or customers; reduce development time; reduce supply chain of customers and  avoid customers needing to add a FPGA on their board.  Non-volatile memory can be added to avoid extra component. This usage is available from 350nm to advanced technology node.

AI applications

Obtain the best performances, area and power consumption by integrating the arithmetic blocks that best target your set of AI algorithms. Outperform existing architectures power cost of calculation – storage within memory by integrating the exact third-party memory within Menta eFPGA IP. Increase energy efficiency by a 10x factor compared to COT FPGA in the same technology node.

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Advantages

100% third party standard cells: fully verifiable within your own flow. 
Limited extra cost.
Can use automotive ready standard cells.
Standard scan chain DfT.
Test coverage in excess of 99.8%.
Fault coverage in excess of 99.5%.
No SRAM bitcells.
No testchip required.
 

Menta delivers 100% third party standard-cells embedded FPGA IPs for SoC, ASIC or ASSP designs. 

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Phone: +33 (0) 9 72 41 03 10

Fax: +33 (0) 9 72 11 33 65

Menta S.A.S, Sophia Antipolis

Les Drakkar, 2405 route des Dolines

06560 Valbonne

France