Menta eFPGA basics

Building flexible SoCs

embedded Field Programmable Gate Array (eFPGA) IPs are based on the same core technology as standalone FPGA devices. Menta eFPGA IPs can be reconfigured at will post production to perform any logic function, based on a configuration file called bitstream.

This bitstream is generated by our dedicated software, Origami Programmer, to map RTL to the eFPGA IP. 

Although sharing same core technologies, eFPGA IPs and COT FPGAs have major differences, both on the application side and technically in the same way that embedded CPUs and COTs CPUs are different. These differences are summarized
here.

A Menta eFPGA IP is a matrix of various blocks that are organized by columns. 
At Menta, we believe that each SoC / ASIC design requires different eFPGA IPs. Therefore, our IPs offer a very high level of customisation.

 

eLB (embedded Logic Block):
 

The eLBs are made of Menta Look-Up-Tables (MLUTs). These are the core configurable blocks able to perform any logic function.
Number of columns and rows is configurable.

 

eMB (embedded Memory Block): (optionnal)
 

embedded Memory Blocks are columns of 3rd party RAM. Number of columns and type and parameters of the RAM are configurable. There can be a mix of memory types.

DSP:​ (optional)
 

Today Menta offers two different DSP blocks: a simple Multiplier ACcumulator (MAC) and the Core DSP (CDSP)


 

eCB (embedded Customer Block): (optional)
 

To optimize performances, power consumption and area for your specific application, Menta offers the possibility to integrate your own arithmetic elements.

 

IOB (Input Output Block):


The number of IO pairs for each IOB is configurable. Each eFPGA IP can offer several thousands data IOs, even for small IPs. 
IOs are only made of a bypassable flop for ASIC/SoC top level timing closure.
Menta IOBs do not require any specific interfaces. Connections can be made to ASIC/SoC IOs, any kind of bus or direct to SRAM or other IPs (CPUs for e.g.).
 

 

Config IOB (Configuration Input Output Block):


​Dedicated interface for configuration sending and readback. This block can be connected to various interfaces such as SPI, JTAG, AHB, AXI, etc.

 

 

DFT IOB (Design for Test Input Output Block):


Dedicated standard scan chain interface for DfT to apply test vectors.